IBM and Siemens Team on Nanostack Transistor Research

Executive Summary

• IBM and Siemens announced a research collaboration aimed at advancing IBM's nanostack transistor architecture, combining IBM's semiconductor device work with Siemens' electronic design automation, process simulation, lithography optimization and manufacturing software expertise, according to IBM Newsroom.
• Nanostack is described by IBM as the industry's first known three-dimensional, nanosheet-based design, vertically stacking and staggering transistors, with nearly 100 billion transistors in a fingernail-sized space at its current 7 angstrom node, per IBM Newsroom.
• IBM demonstrated the viability of the architecture earlier this year; the companies now say additional advances are needed to prepare the technology for manufacturing and production at scale, according to IBM Newsroom.
• The collaboration covers design, simulation and lithography techniques for current and future nanostack generations beyond the 7 angstrom node, including advanced virtual models of nanostack to model performance, optimize designs and address fabrication challenges before chips are built, per IBM Newsroom.

Key Takeaways

• The announcement is a research collaboration, not a production commitment: IBM and Siemens say the work targets the manufacturing and design capabilities needed for future nanostack generations.
• IBM frames nanostack as a scalable transistor platform that shifts device scaling from 2D to 3D, with the 7 angstrom node as the current reference point.
• Siemens' contribution is concentrated in software and simulation: EDA, process simulation, lithography optimization and advanced manufacturing software.
• Virtual modeling is positioned as the near-term deliverable of the collaboration, aimed at resolving fabrication challenges before physical chips are built.

IBM Nanostack Design and the Scaling Problem It Targets

IBM's nanostack architecture is the subject of the collaboration. According to IBM Newsroom, it is the industry's first known three-dimensional, nanosheet-based design that vertically stacks and staggers transistors to pack more of them onto a chip. At its current 7 angstrom node, IBM says the design places nearly 100 billion transistors in a space the size of a fingernail.

The architectural claim rests on two mechanisms described in the announcement. First, stacking and staggering transistors increases device density relative to a purely planar layout. Second, the design unlocks the use of different material combinations within each stacked layer, allowing IBM to optimize the performance and power efficiency of each transistor independently of the others. IBM states that these innovations power substantial leaps in energy efficiency, performance and SRAM scaling.

The framing matters for how the collaboration should be read. IBM says it demonstrated the viability of the nanostack architecture earlier this year. Viability in a research setting is a different milestone from manufacturability, and the announcement is explicit that additional advances are required before the technology can be produced at scale. The 7 angstrom node is the current reference, not a production target already met.

Huiming Bu, Vice President of Silicon Technology R&D at IBM, described nanostack as a scalable transistor platform designed to shift device scaling from 2D to 3D and a path forward for the logic scaling needed to support AI and other emerging technologies over the coming decade. That is IBM's characterization of the architecture's purpose, not an independent measure of progress.

IBM and Siemens Division of Labor in the Research

The collaboration pairs IBM's semiconductor device innovation with Siemens' software and simulation stack. IBM Newsroom lists Siemens' relevant expertise as electronic design automation, process simulation, lithography optimization and advanced manufacturing software. The stated goal is to accelerate development of the manufacturing and design capabilities needed for future nanostack generations.

The work spans design, simulation and lithography techniques for the current node and beyond it. A central element is the development of advanced virtual models of nanostack, which the companies say will be used to model performance, optimize designs and address fabrication challenges before chips are built.

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Ankur Gupta, Executive Vice President, EDA IC Portfolio at Siemens, framed the challenge as one of co-optimization: scaling semiconductors into the angstrom era demands tightly coupled work between device physics, EDA design and manufacturing software, and manufacturing. Gupta described IBM's 3D nanostack design as a leap forward as physical AI places demands on silicon architecture, and characterized Siemens' role in advancing virtual modeling, simulation, lithography and design software optimizations as addressing physical limitations early.

Those statements are attributed positions from the two executives. They describe intended direction, not delivered results from the collaboration, which was announced on the date of the release.

IBM Signals Table

The source does not specify fabrication locations, foundry partners, customer commitments, timelines or investment figures. Those details are absent and are not inferred here.

For deeper context, see our AI Chips analysis: "NVIDIA and Cisco Plan USFP Pluggable Optics for AI Fabrics".

IBM Implementation Risks

The announcement itself identifies the central risk without resolving it: the architecture has been demonstrated as viable, but IBM states that additional advances are needed to prepare it for manufacturing and production at scale. The collaboration is therefore directed at an acknowledged gap rather than at an already-solved problem. Whether virtual modeling and lithography optimization translate into production-ready processes is the question the work is designed to answer, and the source offers no timeline or success criteria.

A second, source-bounded consideration is the coordination requirement Siemens' Gupta describes: device physics, EDA design software and manufacturing must be tightly coupled. Multi-party research of that kind introduces dependency on shared models and methods, and the release does not describe governance, milestones or deliverables. A third is scope: the work is described as research collaboration, which is a different commitment from a supply agreement or a production program. Nothing in the source indicates that either company has committed to volume manufacturing, that a foundry has been engaged, or that customers have been signed.

Practitioners reading the announcement should treat the performance and scaling language as IBM's description of the architecture's intended characteristics, not as independently verified results. No third-party benchmarks, yield data or cost figures appear in the source.

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Editorial independence note: this analysis is based solely on the supplied IBM Newsroom release and does not reflect review, endorsement or input from IBM, Siemens or any other party. Source.

What This Means for Practitioners

For semiconductor procurement and design teams, the practical signal is that angstrom-era scaling is being positioned as a coupled software and device problem rather than a device problem alone. If stacking and staggering transistors becomes the path forward, design flows, simulation models and lithography tooling need to support it, which is where Siemens' stated contribution sits. Buyers evaluating long-term process roadmaps should track whether virtual modeling shortens development cycles in practice, since that is the mechanism the companies claim. No capacity, pricing or availability commitments were disclosed, so this remains a technology-watch item for roadmap planning.